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1 of 30 may 23, 2013 ? 2013 integrated device technology, inc. dsc 6928 idt and the idt logo are regi stered trademarks of integrated device technology, inc. ? device overview the 89HPES4T4G2, a 4-lane 4-port g en2 pci express? switch, is a member of idt?s precise? family of pci express switching solutions. the pes4t4g2 is a peripheral chip that performs pci express base switching with a feature set optimiz ed for servers, storage, communica- tions, and consumer applications. it pr ovides connectivity and switching functions between a pci express upstream port and three downstream ports or peer-to-peer switchi ng between downstream ports. features ? high performance pci express switch ? four gen2 pci express lanes supporting 5 gbps and 2.5 gbps operations ? four switch ports ? one x1 upstream port ? three x1 downstream ports ? low latency cut-through switch architecture ? support for max payload size up to 2kbytes ? supports one virtual channel and eight traffic classes ? pci express base specification revision 2.0 compliant ? flexible architecture with nume rous configuration options ? automatic lane reversal on all ports ? automatic polarity inversion ? ability to load device conf iguration from serial eeprom ? legacy support ? pci compatible intx emulation ? bus locking ? highly integrated solution ? requires no external components ? incorporates on-chip internal memory for packet buffering and queueing ? integrates four 5 gbps embedded serdes with 8b/10b encoder/decoder (no separate transceivers needed) ? receive equalization (rxeq) ? reliability, availability, and serviceability (ras) features ? internal end-to-end parity protecti on on all tlps ensures data integrity even in systems t hat do not implement end-to-end crc (ecrc) ? supports ecrc and advanced error reporting ? all internal data and control rams are secded ecc protected ? supports pci express native hot-plug, hot-swap capable i/o ? compatible with hot-plug i/o expanders used on pc mother- boards ? supports hot-swap block diagram figure 1 internal block diagram 4-port switch core / 4 gen2 pci express lanes frame buffer route table port arbitration scheduler serdes phy logical layer mux / demux transaction layer data link layer (port 0) (port 1) serdes phy logical layer mux / demux transaction layer data link layer serdes phy logical layer mux / demux transaction layer data link layer (port 2) (port 3) serdes phy logical layer transaction layer data link layer mux / demux 89HPES4T4G2 data sheet 4-lane 4-port gen2 pci express? switch
2 of 30 may 23, 2013 idt 89hpes4t4 g2 data sheet ? power management ? utilizes advanced low-power desi gn techniques to achieve low typical power consumption ? support pci power management interface specification (pci- pm 2.0) ? supports device power management states: d0, d3 hot and d3 cold ? support for pci express active state power management (aspm) link state ? supports link power management states: l0, l0s, l1, l2/l3 ready and l3 ? supports pci express power budgeting capability ? configurable serdes power consumption ? supports optional pci-express serdes transmit low-swing voltage mode ? supports numerous serdes transmit voltage margin settings ? unused serdes are disabled ? testability and debug features ? built in pseudo-random bi t stream (prbs) generator ? numerous serdes test modes ? ability to read and write any in ternal register via the smbus ? ability to bypass link training and force any link into any mode ? provides statistics and performance counters ? general purpose input/output pins ? each pin may be individually co nfigured as an input or output ? each pin may be individually co nfigured as an interrupt input ? some pins have selectable alternate functions ? packaged in a 19mm x 19mm, 324-ball bga with 1mm ball spacing product description utilizing standard pci express interconnect the pes4t4g2 provides the most efficient high-performance i/o connectivity device for applica- tions requiring high throughput, low latency and simple board layout. it provides pci express connectivit y across 4 lanes and 4 ports. each lane provides 5 gbps of bandwidth in both directions and is fully compliant with pci express base specification 2.0. the pes4t4g2 is based on a flexib le and efficient layered architec- ture. the pci express layer consists of serdes, physical, data link and transaction layers in compliance with pci express base specification revision 2.0. the pes4t4g2 can operate either as a store and forward or cut-through switch and is designed to switch memory and i/o transac- tions. it supports eight traffic classes (tcs) and one virtual channel (vc) with sophisticated resour ce management to enable efficient switching and i/o connectivity for servers, storage, and embedded processors with limited connectivity. figure 2 i/o expansion application smbus interface the pes4t4g2 contains two smbus interfaces. the slave interface provides full access to the conf iguration registers in the pes4t4g2, allowing every configurati on register in the device to be read or written by an external agent. the master in terface allows the default configura- tion register values of the pes4t4g2 to be overridden following a reset with values programmed in an ex ternal serial eeprom. the master interface is also used by an external hot-plug i/o expander. two pins make up each of the two smbus interfaces. these pins consist of an smbus clock pin and an smbus data pin. the master smbus address is hardwired to 0x 50, and the slave smbus address is hardwired to 0x77. as shown in figure 3, the master and slave smbuses may be used in a unified or split configuration. in the unified configuration, shown in figure 3(a), the master and slave smbuses are tied together and the pes4t4g2 acts both as a smbus master as well as a smbus slave on this bus. this requires that the smbus master or processor that has access to pes4t4g2 registers suppor ts smbus arbitration. in some systems, this smbus master in terface may be implemented using general purpose i/o pins on a proces sor or micro controller, and may not support smbus arbitration. to support these systems, the pes4t4g2 may be configured to operate in a split configuration as shown in figure 3(b). in the split configuration, the master and slave smbuses operate as two independent buses and thus multi- master arbitration is never required. the pes4t4g2 supports reading and writing of the serial eeprom on the master smbus via the slave smbus, allowing in system programming of the serial eeprom. memory memory memory processor memory north bridge pes4t4g2 i/o 4xgbe i/o 4xgbe i/o sata i/o sata pci express slot processor x1 x1 x1 x1
3 of 30 may 23, 2013 idt 89hpes4t4 g2 data sheet figure 3 smbus interface configuration examples hot-plug interface the pes4t4g2 supports pci express hot-plug on each downstream port. to reduce the number of pins required on the device, the pe s4t4g2 utilizes an external i/o expander, such as that used on pc mother boards, connected to the smbus mast er interface. following res et and configura- tion, whenever the state of a hot-plug output needs to be modifi ed, the pes4t4g2 generates an smbus transaction to the i/o expa nder with the new value of all of the outputs. whenever a hot-plug input changes , the i/o expander generates an interrupt which is received on th e ioexpintn input pin (alternate function of gpio) of the pes4t4g2. in response to an i/o expander interrupt, the pes4t4g2 generates an smbus transac tion to read the state of all of the hot-plug inputs from the i/o expander. general purpose input/output the pes4t4g2 provides 7 general purpose inpu t/output (gpio) pins that may be used by the system designer as bit i/o ports. each gpio pin may be configured independently as an input or output through software control. most gpio pins are shared with other on-chip fu nctions. these alter- nate functions may be enabled via software, smbus slav e interface, or serial configuration eeprom. processor pes4t4g2 ssmbclk ssmbdat msmbclk msmbdat smbus master other smbus devices serial eeprom processor pes4t4g2 ssmbclk ssmbdat msmbclk msmbdat smbus master other smbus devices serial eeprom ... ... (a) unified configuration and management bus (b) split configurati on and management buses
4 of 30 may 23, 2013 idt 89hpes4t4 g2 data sheet pin description the following tables list the functions of the pins provided on the pes4t4g2. some of the functions listed may be multiplexed o nto the same pin. the active polarity of a signal is defined using a suffix. signals ending with an ?n? are defi ned as being active, or asserted, when at a logic zero (low) level. all other signals (including clocks, buses, and select lines) will be interpret ed as being active, or asserted, when at a logic one (high) level. signal type name/description pe0rp[0] pe0rn[0] i pci express port 0 serial data receive. differential pci express receive pair for port 0. port 0 is the upstream port. pe0tp[0] pe0tn[0] o pci express port 0 serial data transmit. differential pci express trans- mit pair for port 0. port 0 is the upstream port. pe1rp[0] pe1rn[0] i pci express port 1 serial data receive. differential pci express receive pair for port 1. pe1tp[0] pe1tn[0] o pci express port 1 serial data transmit. differential pci express trans- mit pair for port 1. pe2rp[0] pe2rn[0] i pci express port 2 serial data receive. differential pci express receive pair for port 2. pe2tp[0] pe2tn[0] o pci express port 2 serial data transmit. differential pci express trans- mit pair for port 2. pe3rp[0] pe3rn[0] i pci express port 3 serial data receive. differential pci express receive pair for port 3. pe3tp[0] pe3tn[0] o pci express port 3 serial data transmit. differential pci express trans- mit pair for port 3. perefclkp perefclkn i pci express reference clock. differential reference clock pair input. this clock is used as the reference clock by on-chip plls to generate the clocks required for the system logic and on-chip serdes. the frequency of the dif- ferential reference clock is set at 100mhz. table 1 pci express interface pins signal type name/description msmbclk i/o master smbus clock. this bidirectional signal is used to synchronize transfers on the master smbus which operates at 400 khz. msmbdat i/o master smbus data. this bidirectional signal is used for data on the mas- ter smbus which operates at 400 khz. ssmbclk i/o slave smbus clock. this bidirectional signal is used to synchronize trans- fers on the slave smbus. ssmbdat i/o slave smbus data. this bidirectional signal is used for data on the slave smbus. table 2 smbus interface pins
5 of 30 may 23, 2013 idt 89hpes4t4 g2 data sheet signal type name/description gpio[0] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p2rstn alternate function pin type: output alternate function: reset output for downstream port 2. gpio[1] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. gpio[2] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: ioexpintn0 alternate function pin type: input alternate function: i/o expander interrupt 0 input. gpio[7] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: gpen alternate function pin type: output alternate function: general purpose event (gpe) output gpio[8] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p1rstn alternate function pin type: output alternate function: reset output for downstream port 1 gpio[9] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p3rstn alternate function pin type: output alternate function: reset output for downstream port 3 gpio[10] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. table 3 general purpose i/o pins
6 of 30 may 23, 2013 idt 89hpes4t4 g2 data sheet signal type name/description cclkds i common clock downstream. the assertion of this pin indicates that all downstream ports are using the same clock source as that provided to downstream devices.this bit is used as the initial value of the slot clock configuration bit in all of the link status registers for downstream ports. the value may be overridden by modifying the sclk bit in each down- stream port?s pcielsts register. cclkus i common clock upstream. the assertion of this pin indicates that the upstream port is using the same clock source as the upstream device. this bit is used as the initial value of the slot clock configuration bit in the link status register for the upstream port. the value may be overridden by modifying the sclk bit in the p0_pcielsts register. perstn i fundamental reset. assertion of this signal resets all logic inside pes4t4g2 and initiates a pci express fundamental reset. swmode[2:0] i switch mode. these configuration pins de termine the pes4t4g2 switch operating mode. 0x0 - normal switch mode 0x1 - normal switch mode with serial eeprom initialization 0x2 - through 0x7 reserved these pins should be static and not change following the negation of perstn. table 4 system pins signal type name/description jtag_tck i jtag clock . this is an input test clock used to clock the shifting of data into or out of the boundary scan logic or jtag controller. jtag_tck is independent of the system clock with a nominal 50% duty cycle. jtag_tdi i jtag data input . this is the serial data input to the boundary scan logic or jtag controller. jtag_tdo o jtag data output . this is the serial data shifted out from the boundary scan logic or jtag controller. when no data is being shifted out, this signal is tri-stated. jtag_tms i jtag mode . the value on this signal controls the test mode select of the boundary scan logic or jtag controller. jtag_trst_n i jtag reset . this active low signal asynchronously resets the boundary scan logic and jtag tap controller. an external pull-up on the board is recommended to meet the jtag specification in cases where the tester can access this signal. however, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board table 5 test pins
7 of 30 may 23, 2013 idt 89hpes4t4 g2 data sheet signal type name/description refres0 i/o port 0 external reference resistor. provides a reference for the port 0 serdes bias currents and pll calibration circuitry. a 3 kohm +/- 1% resis- tor should be connected from this pin to ground. refres1 i/o port 1 external reference resistor. provides a reference for the port 1 serdes bias currents and pll calibration circuitry. a 3 kohm +/- 1% resis- tor should be connected from this pin to ground. refres2 i/o port 2 external reference resistor. provides a reference for the port 2 serdes bias currents and pll calibration circuitry. a 3 kohm +/- 1% resis- tor should be connected from this pin to ground. refres3 i/o port 3 external reference resistor. provides a reference for the port 3 serdes bias currents and pll calibration circuitry. a 3 kohm +/- 1% resis- tor should be connected from this pin to ground. v dd core i core v dd. power supply for core logic. v dd i/o i i/o v dd. lvttl i/o buffer power supply. v dd pea i pci express analog power. serdes analog power supply (1.0v). v dd peha i pci express analog high power. serdes analog power supply (2.5v). v dd peta i pci express transmitter analog voltage. serdes transmitter analog power supply (1.0v). v ss i ground. table 6 power, ground, a nd serdes resistor pins
8 of 30 may 23, 2013 idt 89hpes4t4 g2 data sheet pin characteristics note: some input pads of the pes4t4g2 do not contain internal pull-ups or pull-downs. unused inputs should be tied off to appropriate levels. this is especially crit ical for unused control signal inputs which, if le ft floating, could adverse ly affect operation. also, any input pin left floating can cause a slight in crease in power consumption. function pin name type buffer i/o type internal resistor 1 notes pci express inter- face pe0rn[0] i pcie differential 2 serial link pe0rp[0] i pe0tn[0] o pe0tp[0] o pe1rn[0] i pe1rp[0] i pe1tn[0] o pe1tp[0] o pe2rn[0] i pe2rp[0] i pe2tn[0] o pe2tp[0] o pe3rn[0] i pe3rp[0] i pe3tn[0] o pe3tp[0] o perefclkn i hcsl diff. clock input refer to table 8 perefclkp i smbus msmbclk i/o sti 3 pull-up on board msmbdat i/o sti pull-up on board ssmbclk i/o sti pull-up on board ssmbdat i/o sti pull-up on board general purpose i/o gpio[10:7, 2:0] i/o lvttl sti, high drive pull-up system pins cclkds i lvttl input pull-up cclkus i input pull-up perstn i sti swmode[2:0] i input pull-down ejtag / jtag jtag_tck i lvttl sti pull-up jtag_tdi i sti pull-up jtag_tdo o jtag_tms i sti pull-up jtag_trst_n i sti pull-up table 7 pin characteristics (part 1 of 2)
9 of 30 may 23, 2013 idt 89hpes4t4 g2 data sheet serdes reference resistors refres0 i/o analog input refres1 i/o refres2 i/o refres3 i/o 1. internal resistor values under ty pical operating conditions are 92k for pull-up and 90k for pull-down. 2. all receiver pins set the dc common mode voltage to ground. all transmitters must be ac coupled to the media. 3. schmitt trigger input (sti). function pin name type buffer i/o type internal resistor 1 notes table 7 pin characteristics (part 2 of 2)
10 of 30 may 23, 2013 idt 89hpes4t4 g2 data sheet logic diagram ? pes4t4g2 figure 4 pes4t4g2 logic diagram pe0tp[0] reference clocks perefclkp perefclkn jtag_tck gpio[10:7,2:0] 7 general purpose i/o v dd core v dd i/o v dd pea power/ground msmbclk msmbdat ssmbclk ssmbdat master smbus interface slave smbus interface cclkus system pins jtag_tdi jtag_tdo jtag_tms jtag_trst_n jtag pins v ss swmode[2:0] 3 cclkds perstn pe0rp[0] pe0rn[0] pci express switch serdes input pe0tn[0] pci express switch serdes output port 0 port 0 pe1rp[0] pe1rn[0] pci express switch serdes input pe1tp[0] pe1tn[0] pci express switch serdes output port 1 port 1 pe2rp[0] pe2rn[0] pci express switch serdes input pe2tp[0] pe2tn[0] pci express switch serdes output port 2 port 2 pe3rp[0] pe3rn[0] pci express switch serdes input pe3tp[0] pe3tn[0] pci express switch serdes output port 3 port 3 pes4t4g2 refres0 serdes reference resistors refres1 refres2 refres3 v dd peha v dd peta
11 of 30 may 23, 2013 idt 89hpes4t4 g2 data sheet system clock parameters values based on systems running at recommended supply voltage s and operating temperatures, as shown in tables 12 and 14. ac timing characteristics parameter description condition min typical max unit refclk freq input reference clock frequency range 100 100 1 1. the input clock frequency is set at 100 mhz. mhz t c-rise rising edge rate differential 0.6 4 v/ns t c-fall falling edge rate differential 0.6 4 v/ns v ih differential input high voltage differential +150 mv v il differential input low voltage differential -150 mv v cross absolute single-ended crossing point voltage single-ended +250 +550 mv v cross-delta variation of v cross over all rising clock edges single-ended +140 mv v rb ring back voltage margin differential -100 +100 mv t stable time before v rb is allowed differential 500 ps t period-avg average clock period accuracy -300 2800 ppm t period-abs absolute period, including spread-spec- trum and jitter 9.847 10.203 ns t cc-jitter cycle to cycle jitter 150 ps v max absolute maximum input voltage +1.15 v v min absolute minimum input voltage -0.3 v duty cycle duty cycle 40 60 % rise/fall matching single ended rising refclk edge rate ver- sus falling refclk edge rate 20 % z c-dc clock source output dc impedance 40 60 table 8 input clock requirements parameter description gen 1 gen 2 units min 1 typ 1 max 1 min 1 typ 1 max 1 pcie transmit ui unit interval 399.88 400 400.12 199.94 200 200.06 ps t tx-eye minimum tx eye width 0.75 0.75 ui t tx-eye-median-to- max-jitter maximum time between the jitter median and maximum deviation from the median 0.125 ui t tx-rise , t tx-fall tx rise/fall time: 20% - 80% 0.125 0.15 ui t tx- idle-min minimum time in idle 20 20 ui t tx-idle-set-to-idle maximum time to transition to a valid idle after sending an idle ordered set 88 ns table 9 pcie ac timing characteristics (part 1 of 2)
12 of 30 may 23, 2013 idt 89hpes4t4 g2 data sheet t tx-idle-to-diff- data maximum time to transition from valid idle to diff data 8 8 ns t tx-skew transmitter data skew between any 2 lanes 1.3 1.3 ns t min-pulsed minimum instantaneous lone pulse width na 0.9 ui t tx-hf-dj-dd transmitter deterministic jitter > 1.5mhz bandwidth na 0.15 ui t rf-mismatch rise/fall time differential mismatch na 0.1 ui pcie receive ui unit interval 399.88 400 400.12 199.94 200.06 ps t rx-eye (with jitter) minimum receiver eye width (jitter tolerance) 0.4 0.4 ui t rx-eye-medium to max jitter max time between jitter median & max deviation 0.3 ui t rx-skew lane to lane input skew 20 8 ns t rx-hf-rms 1.5 ? 100 mhz rms jitter (common clock) na 3.4 ps t rx-hf-dj-dd maximum tolerable dj by the receiver (common clock) na 88 ps t rx-lf-rms 10 khz to 1.5 mhz rms jitter (common clock) na 4.2 ps t rx-min-pulse minimum receiver instantaneous eye width na 0.6 ui 1. minimum, typical, and maximum values meet the requirements under pci specification 2.0 signal symbol reference edge min max unit timing diagram reference gpio gpio[10:7,2:0] 1 1. gpio signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. tpw 2 2. the values for this symbol were determined by calculation, not by testing. none 50 ? ns table 10 gpio ac timing characteristics parameter description gen 1 gen 2 units min 1 typ 1 max 1 min 1 typ 1 max 1 table 9 pcie ac timing characteristics (part 2 of 2)
13 of 30 may 23, 2013 idt 89hpes4t4 g2 data sheet figure 5 jtag ac timing waveform signal symbol reference edge min max unit timing diagram reference jtag jtag_tck tper_16a none 50.0 ? ns see figure 5. thigh_16a, tlow_16a 10.0 25.0 ns jtag_tms 1 , jtag_tdi 1. the jtag specification, ieee 1149.1, reco mmends that jtag_tms should be held at 1 while the signal applied at jtag_trst_n changes from 0 to 1. otherwise, a race may occur if jtag_trst_n is deasserted (going from low to high) on a rising edge of jtag _tck when jtag_tms is low, because the tap controller might go to eith er the run-test/idle state or stay in the test-logic-reset sta te. tsu_16b jtag_tck rising 2.4 ? ns thld_16b 1.0 ? ns jtag_tdo tdo_16c jtag_tck falling ? 20 ns tdz_16c 2 2. the values for this symbol were determined by calculation, not by testing. ?20ns jtag_trst_n tpw_16d 2 none 25.0 ? ns table 11 jtag ac timing characteristics tpw_16d tdz_16c tdo_16c thld_16b tsu_16b thld_16b tsu_16b tlow_16a tlow_16a tper_16a thigh_16a jtag_tck jtag_tdi jtag_tms jtag_tdo jtag_trst_n
14 of 30 may 23, 2013 idt 89hpes4t4 g2 data sheet recommended operating supply voltages absolute maximum voltage rating warning: for proper and reliable operation in adherenc e with this data sheet, the device s hould not exceed the recommended operating vol tages in table 12. the absolute maximum operating voltages in table 13 are offered to provide guidelines for voltage excursions outsi de the recommended voltage ranges. device functionality is not guaranteed at these c onditions and sustained operation at these values or any expos ure to voltages outside the maximum range may adversely affect device functionality and reliability. power-up/power-down sequence during power supply ramp-up, v dd core must remain at least 1.0v below v dd i/o at all times. there are no other power-up sequence require- ments for the various operating supply voltages. the power-down sequence can occur in any order. recommended operating temperature symbol parameter minimum typical maximum unit v dd core internal logic supply 0.9 1.0 1.1 v v dd i/o i/o supply except for serd es lvpecl/cml 3.135 3.3 3.465 v v dd pea 1 1. v dd pea and v dd peta should have no more than 25mv peak-peak ac power supply noise superimposed on the 1.0v nominal dc value. pci express analog power 0.95 1.0 1.1 v v dd peha 2 2. v dd peha should have no more than 50mv peak-peak ac power supply noise superimposed on the 2.5v nominal dc value. pci express analog high power 2.25 2.5 2.75 v v dd peta 1 pci express transmitter analog voltage 0.95 1.0 1.1 v v ss common ground 0 0 0 v table 12 pes4t4g2 operating voltages core supply pcie analog supply pcie analog high supply pcie transmitter supply i/o supply 1.5v 1.5v 4.6v 1.5v 4.6v table 13 pes4t4g2 absolute maximum voltage rating grade temperature commercial 0 c to +70 c ambient industrial -40 c to +85 c ambient table 14 pes4t4g2 operating temperatures
15 of 30 may 23, 2013 idt 89hpes4t4 g2 data sheet power consumption typical power is measured under the following conditions: 25c am bient, 35% total link usage on all ports, typical voltages def ined in table 12 (and also listed below). maximum power is measured under the follow ing conditions: 70c ambient, 85% total li nk usage on all ports, maximum voltages def ined in table 12 (and also listed below). thermal considerations this section describes thermal cons iderations for the pes4t4g2 (19mm 2 fcbga324 package). the data in table 16 below contains information that is relevant to the thermal performance of the pes4t4g2 switch. note: it is important for the reliability of this device in any us er environment that the juncti on temperature not exceed the t j(max) value specified in table 16. consequently, the effect ive junction to ambient thermal resistance ( ja ) for the worst case scenario must be maintained below the value determined by the formula: ja = (t j(max) - t a(max) )/p given that the values of t j(max) , t a(max) , and p are known, the value of desired ja becomes a known entity to the system designer. how to achieve the desired ja is left up to the board or system designer, but in gen eral, it can be achieved by adding the effects of jc (value provided in table 16), thermal re sistance of the chosen adhesive ( cs ), that of the heat sink ( sa ), amount of airflow, and properties of the circuit board (number of layers and size of the board). as a general guideline, this device will not need a heat sink if the bo ard has 8 or more layers and the board size is larger than 4" x12" and airflow in excess of 0.5 m/s is available. it is strongly recommended that users perform their own thermal analysis for thei r own board and system design scenarios. number of active lanes per port core supply pcie analog supply pcie analog high supply pcie termin- ation supply i/o supply total typ 1.0v max 1.1v typ 1.0v max 1.1v typ 2.5v max 2.75v typ 1.0v max 1.1v typ 3.3v max 3.465v typ power max power 1/1/1/1 full swing ma 375 700 703 752 74 83 360 429 2 3 watts 0.38 0.77 0.70 0.83 0.19 0.23 0.36 0.47 0.007 0.01 1.63 2.31 1/1/1/1 half swing ma 375 700 703 752 74 83 180 215 2 3 watts 0.38 0.77 0.70 0.83 0.19 0.23 0.18 0.24 0.007 0.01 1.45 2.07 table 15 pes4t4g2 power consumption symbol parameter value units conditions t j(max) junction temperature 125 o cmaximum t a(max) ambient temperature 70 o cmaximum ja(effective) effective thermal resistance, junction-to-ambient 16.8 o c/w zero air flow 10.1 o c/w 1 m/s air flow 9.2 o c/w 2 m/s air flow jb thermal resistance, junction-to-board 4.1 o c/w jc thermal resistance, junction-to-case 0.3 o c/w p power dissipation of the device 2.31 watts maximum table 16 thermal specifications for pes4t4g2, 19x19 mm fcbga3 24 package
16 of 30 may 23, 2013 idt 89hpes4t4 g2 data sheet dc electrical characteristics values based on systems running at recommended su pply voltages, as shown in table 12. note: see table 7, pin characteristic s, for a complete i/o listing. i/o type parameter description gen1 gen2 unit condi- tions min 1 typ 1 max 1 min 1 typ 1 max 1 serial link pcie transmit v tx-diffp-p differential peak-to-peak output voltage 800 1200 800 1200 mv v tx-diffp-p-low low-drive differential peak to peak output voltage 400 1200 400 1200 mv v tx-de-ratio- 3.5db de-emphasized differential output voltage -3 -4 -3.0 -3.5 -4.0 db v tx-de-ratio- 6.0db de-emphasized differential output voltage na -5.5 -6.0 -6.5 db v tx-dc-cm dc common mode voltage 0 3.6 0 3.6 v v tx-cm-acp rms ac peak common mode output voltage 20 mv v tx-cm-dc-active- idle-delta abs delta of dc common mode voltage between l0 and idle 100 100 mv v tx-cm-dc-line- delta abs delta of dc common mode voltage between d+ and d- 25 25 mv v tx-idle-diffp electrical idle diff peak output 20 20 mv rl tx-diff transmitter differential return loss 10 10 db 0.05 - 1.25ghz 8 db 1.25 - 2.5ghz rl tx-cm transmitter common mode return loss 66db z tx-diff-dc dc differential tx impedance 80 100 120 120 vtx-cm-acpp peak-peak ac common na 100 mv v tx-dc-cm transmit driver dc common mode voltage 0 3.6 0 3.6 v v tx-rcv-detect the amount of voltage change allowed during receiver detec- tion 600 600 mv i tx-short transmitter short circuit current limit 090 90ma table 17 dc electrical characteristics (part 1 of 2)
17 of 30 may 23, 2013 idt 89hpes4t4 g2 data sheet serial link (cont.) pcie receive v rx-diffp-p differential input voltage (peak-to- peak) 175 1200 120 1200 mv rl rx-diff receiver differential return loss 10 10 db 0.05 - 1.25ghz 8 1.25 - 2.5ghz rl rx-cm receiver common mode return loss 66db z rx-diff-dc differential input impedance (dc) 80 100 120 refer to return loss spec z rx--dc dc common mode impedance 40 50 60 40 60 z rx-comm-dc powered down input common mode impedance (dc) 200k 350k 50k z rx-high-imp-dc- pos dc input cm input impedance for v>0 during reset or power down 50k 50k z rx-high-imp-dc- neg dc input cm input impedance for v<0 during reset or power down 1.0k 1.0k v rx-idle-det- diffp-p electrical idle detect threshold 65 175 65 175 mv v rx-cm-acp receiver ac common-mode peak voltage 150 150 mv v rx-cm-acp pcie refclk c in input capacitance 1.5 ? 1.5 ? pf other i/os low drive output i ol ?2.5? ?2.5 ? mav ol = 0.4v i oh ?-5.5? ?-5.5 ? mav oh = 1.5v high drive output i ol ? 12.0 ? ? 12.0 ? ma v ol = 0.4v i oh ? -20.0 ? ? -20.0 ? ma v oh = 1.5v schmitt trig- ger input (sti) v il -0.3 ? 0.8 -0.3 ? 0.8 v ? v ih 2.0 ? v dd i/o + 0.5 2.0 ? v dd i/o + 0.5 v? input v il -0.3 ? 0.8 -0.3 ? 0.8 v ? v ih 2.0 ? v dd i/o + 0.5 2.0 ? v dd i/o + 0.5 v? capacitance c in ??8.5??8.5pf ? leakage inputs ? ? + 10 ? ? + 10 av dd i/o (max) i/o leak w / o pull-ups/downs ??+ 10 ? ? + 10 av dd i/o (max) i/o leak with pull-ups/downs ??+ 80 ? ? + 80 av dd i/o (max) 1. minimum, typical, and maximum values meet the requirements under pci specification 2.0. i/o type parameter description gen1 gen2 unit condi- tions min 1 typ 1 max 1 min 1 typ 1 max 1 table 17 dc electrical characteristics (part 2 of 2)
18 of 30 may 23, 2013 idt 89hpes4t4 g2 data sheet package pinout ? 324-bga signal pinout for pes4t4g2 the following table lists the pin number s and signal names for the pes4t4g2 device. pin function alt pin function alt pin function alt pin function alt a1 v ss b17 nc d15 v dd core f13 v ss a2 v dd i/o b18 nc d16 v ss f14 nc a3 v dd i/o c1 nc d17 v ss f15 nc a4 v dd i/o c2 nc d18 v ss f16 v ss a5 v ss c3 v ss e1 nc f17 nc a6 v dd i/o c4 nc e2 nc f18 nc a7 v ss c5 nc e3 v ss g1 v ss a8 jtag_tdi c6 v ss e4 nc g2 v ss a9 msmbdat c7 jtag_tck e5 nc g3 v ss a10 v dd i/o c8 jtag_trst_n e6 v dd core g4 v dd core a11 v ss c9 ssmbdat e7 v dd core g5 v dd core a12 gpio_00 1 c10 cclkds e8 v dd core g6 v dd pea a13 v dd i/o c11 swmode_2 e9 v ss g7 v dd pea a14 v dd i/o c12 gpio_02 1 e10 v dd core g8 v dd core a15 v ss c13 gpio_09 1 e11 v dd core g9 v dd core a16 v ss c14 nc e12 v dd core g10 v dd core a17 v dd i/o c15 nc e13 v dd core g11 v ss a18 v dd i/o c16 v ss e14 nc g12 v dd pea b1 nc c17 nc e15 nc g13 v dd pea b2 nc c18 nc e16 v ss g14 v dd core b3 v ss d1 v ss e17 nc g15 v dd core b4 nc d2 v ss e18 nc g16 v ss b5 nc d3 v ss f1 pe3tp00 g17 v ss b6 v dd i/o d4 v dd core f2 pe3tn00 g18 v ss b7 v dd i/o d5 v dd core f3 v ss h1 nc b8 jtag_tms d6 v ss f4 pe3rp00 h2 nc b9 ssmbclk d7 jtag_tdo f5 pe3rn00 h3 v ss b10 v dd i/o d8 msmbclk f6 v ss h4 nc b11 swmode_1 d9 cclkus f7 v ss h5 nc b12 gpio_01 d10 swmode_0 f8 v dd core h6 v dd pea b13 gpio_10 d11 perstn f9 v ss h7 v dd pea b14 nc d12 gpio_07 1 f10 v dd core h8 v dd core b15 nc d13 gpio_08 1 f11 v ss h9 v dd core b16 v ss d14 v dd core f12 v ss h10 v dd core h11 v ss k13 v dd peta m15 nc p17 v dd core h12 v dd pea k14 v dd core m16 v ss p18 v ss table 18 pes4t4g2 324-pin si gnal pin-out (part 1 of 3)
19 of 30 may 23, 2013 idt 89hpes4t4 g2 data sheet h13 v dd pea k15 nc m17 nc r1 v ss h14 nc k16 v ss m18 nc r2 v dd core h15 nc k17 nc n1 v ss r3 v dd core h16 v ss k18 nc n2 v ss r4 nc h17 nc l1 nc n3 v ss r5 nc h18 nc l2 nc n4 v dd core r6 nc j1 nc l3 v ss n5 v dd core r7 nc j2 nc l4 nc n6 v ss r8 pe1rp00 j3 v ss l5 nc n7 v ss r9 v dd core j4 nc l6 v dd peta n8 v dd pea r10 nc j5 nc l7 v dd peta n9 v dd peha r11 nc j6 v dd peha l8 v dd pea n10 v dd peta r12 v dd core j7 v dd peha l9 v dd peha n11 v dd pea r13 nc j8 v dd core l10 v dd peta n12 v dd peha r14 pe0rp00 j9 v ss l11 v dd pea n13 v ss r15 v dd core j10 v dd core l12 v dd peha n14 v ss r16 v dd core j11 v ss l13 v dd peta n15 v dd core r17 v dd core j12 v dd peha l14 nc n16 v ss r18 v ss j13 v dd peha l15 nc n17 v ss t1 v ss j14 nc l16 v ss n18 v ss t2 v ss j15 nc l17 nc p1 v ss t3 v ss j16 v ss l18 nc p2 v dd core t4 v ss j17 nc m1 pe2tp00 p3 v dd core t5 v ss j18 nc m2 pe2tn00 p4 nc t6 v ss k1 refres2 m3 v ss p5 nc t7 v ss k2 refres3 m4 pe2rp00 p6 v dd core t8 v ss k3 v ss m5 pe2rn00 p7 nc t9 v ss k4 v dd core m6 v dd peta p8 pe1rn00 t10 v ss k5 v dd core m7 v dd peta p9 v dd core t11 v ss k6 v dd peta m8 v dd pea p10 nc t12 v ss k7 v dd peta m9 v dd peha p11 nc t13 v ss k8 v dd core m10 v dd peta p12 v dd core t14 v ss k9 v ss m11 v dd pea p13 nc t15 v ss k10 v dd core m12 v dd peha p14 pe0rn00 t16 v ss k11 v ss m13 v ss p15 v dd core t17 v ss k12 v dd peta m14 nc p16 v dd core t18 v ss u1 v ss u10 nc v1 v ss v10 nc u2 perefclkn u11 nc v2 perefclkp v11 nc pin function alt pin function alt pin function alt pin function alt table 18 pes4t4g2 324-pin si gnal pin-out (part 2 of 3)
20 of 30 may 23, 2013 idt 89hpes4t4 g2 data sheet alternate signal functions no connection pins u3 v ss u12 v ss v3 v ss v12 v ss u4 nc u13 nc v4 nc v13 nc u5 nc u14 pe0tn00 v5 nc v14 pe0tp00 u6 refres1 u15 v ss v6 refres0 v15 v ss u7 nc u16 v ss v7 nc v16 v ss u8 pe1tn00 u17 v ss v8 pe1tp00 v17 v ss u9 v ss u18 v ss v9 v ss v18 v ss pin gpio alternate a12 gpio_00 p2rstn c12 gpio_02 ioexpintn0 d12 gpio_07 gpen d13 gpio_08 p1rstn c13 gpio_09 p3rstn table 19 pes4t4g2 alternate signal functions nc pins nc pins nc pins nc pins nc pins nc pins b1 c18 h4 k17 p5 u10 b2 e1 h5 k18 p7 u11 b4 e2 h14 l1 p10 u13 b5 e4 h15 l2 p11 v4 b14 e5 h17 l4 p13 v5 b15 e14 h18 l5 r4 v7 b17 e15 j1 l14 r5 v10 b18 e17 j2 l15 r6 v11 c1 e18 j4 l17 r7 v13 c2 f14 j5 l18 r10 c4 f15 j14 m14 r11 c5 f17 j15 m15 r13 c14f18j17m17 u4 c15 h1 j18 m18 u5 c17 h2 k15 p4 u7 table 20 pes4t4g2 no connection pins pin function alt pin function alt pin function alt pin function alt table 18 pes4t4g2 324-pin si gnal pin-out (part 3 of 3)
21 of 30 may 23, 2013 idt 89hpes4t4 g2 data sheet power pins v dd core v dd core v dd core v dd i/o v dd pea v dd peha v dd peta d4 g9 n15 a2 g6 j6 k6 d5 g10 p2 a3 g7 j7 k7 d14 g14 p3 a4 g12 j12 k12 d15 g15 p6 a6 g13 j13 k13 e6 h8 p9 a10 h6 l9 l6 e7 h9 p12 a13 h7 l12 l7 e8 h10 p15 a14 h12 m9 l10 e10 j8 p16 a17 h13 m12 l13 e11 j10 p17 a18 l8 n9 m6 e12 k4 r2 b6 l11 n12 m7 e13 k5 r3 b7 m8 m10 f8 k8 r9 b10 m11 n10 f10 k10 r12 n8 g4 k14 r15 n11 g5 n4 r16 g8 n5 r17 table 21 pes4t4g2 power pins
22 of 30 may 23, 2013 idt 89hpes4t4 g2 data sheet ground pins v ss v ss v ss v ss v ss v ss a1 d18 g17 m16 t3 u3 a5 e3 g18 n1 t4 u9 a7 e9 h3 n2 t5 u12 a11 e16 h11 n3 t6 u15 a15 f3 h16 n6 t7 u16 a16 f6 j3 n7 t8 u17 b3 f7 j9 n13 t9 u18 b16 f9 j11 n14 t10 v1 c3 f11 j16 n16 t11 v3 c6 f12 k3 n17 t12 v9 c16 f13 k9 n18 t13 v12 d1 f16 k11 p1 t14 v15 d2 g1 k16 p18 t15 v16 d3 g2 l3 r1 t16 v17 d6 g3 l16 r18 t17 v18 d16 g11 m3 t1 t18 d17 g16 m13 t2 u1 table 22 pes4t4g2 ground pins
23 of 30 may 23, 2013 idt 89hpes4t4 g2 data sheet signals listed alphabetically signal name i/o type location signal category cclkds i c10 system cclkus i d9 gpio_00 i/o a12 general purpose input/output gpio_01 i/o b12 gpio_02 i/o c12 gpio_07 i/o d12 gpio_08 i/o d13 gpio_09 i/o c13 gpio_10 i/o b13 jtag_tck i c7 jtag jtag_tdi i a8 jtag_tdo o d7 jtag_tms i b8 jtag_trst_n i c8 msmbclk i/o d8 smbus msmbdat i/o a9 no connection see table 20 pe0rn00 i p14 pci express pe0rp00 i r14 pe0tn00 o u14 pe0tp00 o v14 pe1rn00 i p8 pe1rp00 i r8 pe1tn00 o u8 pe1tp00 o v8 pe2rn00 i m5 pe2rp00 i m4 pe2tn00 o m2 pe2tp00 o m1 pe3rn00 i f5 pe3rp00 i f4 pe3tn00 o f2 pe3tp00 o f1 table 23 89pes4t4g2 alphabetical signal list (part 1 of 2)
24 of 30 may 23, 2013 idt 89hpes4t4 g2 data sheet perefclkn i u2 pci express (cont.) perefclkp i v2 perstn i d11 system refres0 i/o v6 serdes reference resistors refres1 i/o u6 refres2 i/o k1 refres3 i/o k2 ssmbclk i/o b9 smbus ssmbdat i/o c9 swmode_0 i d10 system swmode_1 i b11 swmode_2 i c11 v dd core, v dd i/o, v dd pea, v dd peha, v dd peta see table 21 for a listing of power pins. v ss see table 22 for a listing of ground pins. signal name i/o type location signal category table 23 89pes4t4g2 alphabetical signal list (part 2 of 2)
25 of 30 may 23, 2013 idt 89hpes4t4 g2 data sheet pes4t4g2 ? package trace length signal name conductor length (microns) pe0rn00 6476.76 pe0rp00 6852.44 pe0tn00 9779.14 pe0tp00 9830.77 pe1rn00 3844.19 pe1rp00 4219.88 pe1tn00 7518.88 pe1tp00 7605.87 pe2rn00 2227.99 pe2rp00 2600.58 pe2tn00 5462.64 pe2tp00 5576.55 pe3rn00 9181.06 pe3rp00 9541.52 pe3tn00 10606.88 pe3tp00 10747.72 perefclkn 12558.62 perefclkp 12641.05 table 24 signal trace length
26 of 30 may 23, 2013 idt 89hpes4t4 g2 data sheet pes4t4g2 pinout ? top view 1 2 3 4 5 6 7 8 9 10111213141516 vss (ground) v dd core (power) a b v dd i/o (power) 17 18 c d e f g h j k l m n p r t u v v dd peta (power) v dd pea (power) v dd peha (power) signals 12345678910111213141516 17 18 a b c d e f g h j k l m n p r t u v x no connect x x x x x x x x x x x x
27 of 30 may 23, 2013 idt 89hpes4t4 g2 data sheet pes4t4g2 package drawi ng ? 324-pin al324/ar324
28 of 30 may 23, 2013 idt 89hpes4t4 g2 data sheet pes4t4g2 package drawing ? page two
29 of 30 may 23, 2013 idt 89hpes4t4 g2 data sheet revision history january 15, 2009 : publication of final data sheet. february 11, 2009 : revised ac timing characteristics table and dc el ectrical characteristics table to correct typos. march 6, 2009 : added industrial temperature. april 7, 2009 : in valid combinations, changed zb to zc silicon for comme rcial temperature. april 17, 2009 : in table 15, power dissi pation value was changed to 2.31. february 2, 2010 : added new section absolute maximum voltage rating with table. september 13, 2010 : in table 7, changed buffer type for pci express from cm l to pcie differential and changed reference clocks to hcsl. march 30, 2011 : in table 12, added vddpeta to footnote #1. may 23, 2013 : in the features section, added reference to secded ecc under reliability, avail ability, serviceability bullet.
30 of 30 may 23, 2013 idt 89hpes4t4 g2 data sheet corporate headquarters 6024 silver creek valley road san jose, ca 95138 for sales: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for tech support: email: ssdhelp@idt.com phone: 408-284-8208 ? ordering information valid combinations 89HPES4T4G2zcal 324-ball fcbga pac kage, commercial temperature 89HPES4T4G2zcalg 324-ball green fcbga package, commerci al temperature 89HPES4T4G2zcali 324-ball fcbga pac kage, industrial temperature 89HPES4T4G2zcalgi 324-ball green fcbg a package, industr ial temperature nn a aaa nan aa a operating voltage device family product package temp range h product family 89 serial switching product 324-ball fcbga al 4t4 4-lane, 4-port 1.0v +/- 0.1v core voltage detail pci express switch pes legend a = alpha character n = numeric character 324-ball fcbga, green alg aa device revision an generation series g2 pcie gen 2 zc zc revision blank commercial temperature (0c to +70c ambient) i industrial temperature (-40 c to +85 c ambient)

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